module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);

    parameter IDLE = 4'd0;
    parameter D1_1 = 4'd1;
    parameter D1_2 = 4'd2;
    parameter D1_3 = 4'd3;
    parameter D1_4 = 4'd4;
    parameter D1_5 = 4'd5;
    parameter D1_6 = 4'd6;
    parameter DISC = 4'd7;
    parameter FLAG = 4'd8;
    parameter ERR = 4'd9;

    reg	[3:0]	state;
    reg	[3:0]	next_state;
    
    always @(posedge clk) begin
        if(reset) begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    always @(*) begin
        case(state)
            IDLE:begin
                if(in) begin
                    next_state = D1_1;
                end
                else begin
                    next_state = IDLE;
                end
            end
            D1_1:begin
                if(in) begin
                    next_state = D1_2;
                end
                else begin
                    next_state = IDLE;
                end
            end
            D1_2:begin
                if(in) begin
                    next_state = D1_3;
                end
                else begin
                    next_state = IDLE;
                end
            end
            D1_3:begin
                if(in) begin
                    next_state = D1_4;
                end
                else begin
                    next_state = IDLE;
                end
            end
            D1_4:begin
                if(in) begin
                    next_state = D1_5;
                end
                else begin
                    next_state = IDLE;
                end
            end
            D1_5:begin
                if(in) begin
                    next_state = D1_6;
                end
                else begin
                    next_state = DISC;
                end
            end
            D1_6:begin
                if(in) begin
                    next_state = ERR;
                end
                else begin
                    next_state = FLAG;
                end
            end
            DISC:begin
                if(in) begin
                    next_state = D1_1;
                end
                else begin
                	next_state = IDLE;
                end
            end
            FLAG:begin
                if(in) begin
                    next_state = D1_1;
                end
                else begin
                	next_state = IDLE;
                end
            end
            ERR:begin
                if(in) begin
                    next_state = ERR;
                end
                else begin
                    next_state = IDLE;
                end
            end
            default:next_state = IDLE;
        endcase
    end
    
    assign disc = (state == DISC);
    assign flag = (state == FLAG);
    assign err = (state == ERR);
    
endmodule
